Introduction of modules (block, module)

Catalog

Module structure

Data types and their constants and variables

Operators and expressions

Module structure

Module composition ： One part describes the interface （ Port definition 、I/O explain 、 The internal signal says ）, The other part describes the logic function （ Function definition ）.

When referencing a module , Port connection mode ：

1. Module name （ Connection port 1 Signal name , Connection port 2 Signal name ……）

2. Module name （. port 1 name （ Connecting signals 1 name ）,. port 2 name （ Connecting signals 2 name ）

/*I/O The description can also be in the Port declaration statement */
module module_name(input port1,input port2,……
    output port1,output port2……);

The internal signal says

reg [width-1:0] R Variable 1,R Variable 2……;
wire [width-1:0] W Variable 1,W Variable 2……;

Function definition

1. use assign Statement     The variable can be reg（ Is it because of the continuous assignment statement of the procedure ）, Commonly used in combinatorial logic

2. Using example components       The module referenced by the instance , Ports can be connected to the corresponding inputs of other modules through connections with different names or register type variables 、 Output signal terminal

3. always block         The variable needs to be reg      The statements in the block are sequential statements , Sequential execution , So we call this kind of block Process block （ It can describe combinatorial logic , It can also describe temporal logic ）

/*verilog All process blocks in the module （ Such as always、initial block ）、 Continuous assignment statement 、 Instance references are parallel */


assign a=b&c;                       //assign
and #2 u1(q,a,b);                   // Instance component 
/*  Asynchronous reset , The reset signal is the trigger signal , No matter what the clock signal is , Can be reset ; Synchronous reset , Only the clock signal is the trigger signal , Only when a certain clock triggers , Reset will happen */
[email protected](posege clk or posedge clr)  //always block    
                                     
    begin
        if (clr) q<=0;
            else if (en) q<=d;
    end

Data types and their constants and variables

Constant （ An amount that cannot be changed ）

Numbers

1. Integers

The way of expression ：

< A wide >< Base number >< Numbers > Comprehensive description             The bit width indicates the exact number of digits of a number , The width of a binary bit is 1, One                                                                             individual 16 The hexadecimal bit width is 4   8‘ha2

< Base number >< Numbers > The digital bit width adopts the default bit width （ The machine system decides , At least 32 position ）

< Numbers > Use default base （ Decimal system ）

2.x and z（？） value     One x It can represent a binary , octal 、 Hexadecimal  

3. negative   Put a minus sign at the beginning of the expression

4. Underline Separation improves readability    8’b_0011_1010

Parameters （parameter） type

Constants in the form of identifiers   It is often used to define delay time and variable width

parameter Width=1,Polarity=1
/*   adopt #(n,n) Change parameters   */            
Decode  #(4,0) D1(A4,F16)  // The parameter changes to 4,0   
Decode #(5) D2(A5,F32)     // The parameter changes to 5,1

/* When changing the parameters of another module in one module , Need to use defparam command */

Variable

wire

        Network data type （wire、tri type ）, Can't store values . If not connected to the drive ( Such as door or continuous assignment statement assign), Then the variable is in the high resistance state .wire It is usually used to represent a single door drive or continuous assignment ,tri Type variable is used to represent the network data type driven by multiple drivers . If logic strength is not defined , Under multiple driving sources , Logical values will conflict 、 Thus, an uncertain value is generated .

        verilog Enter... In the program module 、 The output signal type is automatically defined as... By default wire type .wire It can be used as input to any equation , Can also be used as assign And the output of instance components .

The module referenced by the instance , Its port can be connected to the corresponding input of other modules through different connection lines or register type variables 、 Output signal terminal .

reg  

         Abstraction of data storage unit , Register data type .reg The default initial value is an indefinite value x, Often represents a trigger .always Each signal assigned in the module must be defined as reg, It only means that the defined signal is used in always In module , Not to say that reg Type a signal must be the output of a register or trigger .

         about reg Type data , The function of the assignment statement is like changing the value of the storage unit of a group of triggers .reg When type data is an operand in an expression , Its value is treated as an unsigned value , It's a positive value . If the start register is assigned a value -1, The value in the expression is considered 15.

memory type

        By expanding reg The address range of the data type is generated .

reg [7:0] mema [255:0]   //256 individual 8 Bit register , Address range is 0 To 255

reg [n-1:0] rega;          // One n Bit register                                        rega=0;// legal

reg mema [n-1:0];       // One by n A memory composed of one bit registers        mema=0; // illegal

Operators and expressions

Basic arithmetic operators

<= When used as a comparison operator, it is binocular operation , When used as blocking assignment, it is monocular operation , Only on the right is the operand .

An operator

Bitwise XOR （^）x And any value XOR is x; It is the same as or （^~） Is prior XOR , Reverse later .

Bit operations of different lengths , The system will automatically align the right ends of the two .