CPU The function and structure of

CPU The function of

1. Command control . Complete the command 、 Analyzing and executing instructions , The sequence control of the program .

2. Operational control . The function of an instruction is often realized by the combination of several operation signals .CPU Manage and generate the operation signal of each instruction fetched from memory , Send various operation signals to corresponding parts , In order to control these parts according to the command to carry out the action .

3. time control . Time control of various operations . Time control shall provide due control signals for each instruction in chronological order .

4. The data processing . Arithmetic and logic operations on data .

5. Interrupt handling . To deal with the abnormal situation and special request in the process of computer operation .

Functions of arithmetic unit and controller

Arithmetic unit ： Process the data

controller ： Coordinate and control the sequence of instructions for the execution of programs by computer components , The basic functions include taking instructions 、 Analysis instructions 、 Execution instruction

• Take command : Automatically form instruction address ; Automatically issue the command to take the instruction .
• Analysis instructions : Opcode decoding ( Analyze what this command is going to do ); The valid address of the generated operands .
• Execution instruction : According to the analysis instructions “ Operation command ” and “ Operand address ”, Form operation signal control sequence , Control arithmetic unit 、 Memory and I/O The equipment completes the corresponding operation .
• Interrupt handling : Management bus and I / O ; Handling exceptions ( Such as power failure ) And special requests ( If the printer requests to print a line of characters ).

Basic structure of arithmetic unit

1. Arithmetic logic unit : The main function is to do arithmetic / Logical operations .

2. General register group : Such as AX、BX、CX、DX、SP etc. , Used to store operands ( Including source operands 、 Destination operands and intermediate results ) And all kinds of address information, etc .SP It's a stack pointer , Used to indicate the address at the top of the stack . The number of digits is equal to the machine word length , Easy to operate and control .

Dedicated data path side requirements : Arrange the connection line according to the flow direction of data and address in the process of instruction execution .

If connected directly with wires , It is equivalent to multiple registers simultaneously and all the way to ALU To transmit data

resolvent 1. A multiplexer is used to select one output according to the control signal

resolvent 2. Three state gate can be used to control whether each channel outputs

Higher performance , There is basically no data conflict , But the structure is complex , Large amount of hardware , It's not easy to achieve .

CPU Internal single bus mode : Connect the input and output of all registers to a common path .

Simple structure , Easy to implement , But there are many conflicts in data transmission , Low performance .

3. Temporary register : Used to temporarily store data read from main memory , This data cannot be stored in the general register , Otherwise, it will destroy its original content . Such as : The two operands are from main memory and R., The final result is saved back R., Then the operands obtained from main memory are directly put into the register , It will not destroy the pre operation R. The content of .

4. Accumulation register : It's a general-purpose register , For temporary storage ALU The result information of the operation , It is used to implement addition operation .

5. Program status word register : All kinds of state information established by the result of arithmetic logic operation instruction or test instruction are retained , Such as overflow flag (OP)、 sign indicator （SF)、 Zero mark (ZF）、 Carry mark (CF） etc. .PSW These bits participate in and determine the formation of micro operations . It consists of two parts , First, the status flag , Twenty control signs .

6. Shifter : Shift the result .

The basic structure of the controller

1. Program counter PC: Used to indicate the location of the next instruction in main memory .CPU It is based on PC To fetch instructions from main memory . Because the instructions in the program （ Usually ） It's sequential , therefore PC It has self increasing function . The number of bits of the program counter is equal to the number of bits of the memory address , And the memory address depends on the capacity of the memory .

2. Instruction register IR: It is used to save the currently executing instruction . No user intervention is required , Transparent to users . The number of bits depends on the instruction word length .

3. Instruction decoder : Only the opcode field is decoded , Provide specific operation signals to the controller .

4. Micromanipulation signal generator : according to IR The content of （ Instructions ）、PSW The content of （ State information ） Just in time signals , Produce all kinds of control signals needed to control the whole computer system , Its structure has two kinds of combinational logic and storage logic .

5. Sequential systems : Used to generate all kinds of timing signals , They are all made up of a unified clock (CLOCK） Divide the frequency to get .

6. Memory address register MDR: It is used to store the address of the main memory unit to be accessed .

7. Memory data register MAR: It is used to store information written to or read from main memory .

The controller consists of program counter PC, Instruction register IR, Memory address register MAR, Memory data register MDR, Instruction decoder , Sequential circuit and micro operation generator .

Instruction execution process

Instruction cycle

Instruction cycle :CPU The total time required to fetch and execute each instruction from main memory .

Instruction cycles often take several Machine cycle To express , Machine cycle is also called CPU cycle .

A machine cycle contains several clock cycles （ Also called beat 、T Cycle or CPU Clock cycle , It is CPU The most basic unit of operation ）.

The number of machine cycles per instruction cycle can vary , The number of beats per machine cycle can also vary .

The difference of various cycles

• The clock cycle is the smallest unit of time for computer operation , Determined by the dominant frequency of the computer , Is the reciprocal of the dominant frequency . The working pulse is the smallest time unit of the controller , rise i Timed trigger action , A clock cycle has a working pulse .
• The instruction cycle can consist of multiple CPU Cycle composition .
• CPU Cycle is machine cycle , Contains several clock cycles .
• Access cycle refers to two independent memory operations of the memory （ Two consecutive read or write operations ） Minimum interval required between .

Instruction cycle flow

All four work cycles have CPU Memory access operation , It's just that the purpose of deposit access is different . The fetch cycle is to fetch instructions , The inter address period is to get a valid address , The execution cycle is for fetching operands , Interrupt cycle is to save program breakpoints .

Instruction cycle data flow - Take the period

The first machine cycle of the instruction cycle is the fetch cycle , That is, fetch the instruction word from the main memory .

1. The current instruction address is sent to the memory address register , Remember to do :(PC)→MAR

2.CU Send out control signals , Transfer to main memory via control bus , Here's the read signal , Remember to do :1→R

3. take MAR The contents of the main memory are sent to... Via the data bus MDR, Remember to do :M(MAR)→ MDR

4.CU Send out control signals , Form the next instruction address , Remember to do :(PC)+1 →PC

After taking the finger ,PC Automatic addition 1, In the execution cycle , If PC It needs to be modified to jump to the address , You need to +1

Instruction cycle data flow - Interdigital period

1. Send the address code of the instruction to MAR, Remember to do : Ad(IR) →MAR or Ad(MDR)→MAR

2.CU Send out control signals , Start the main memory to read , Remember to do :1→R

3. take MAR The contents of the main memory are sent to... Via the data bus MDR, Remember to do :M(MAR)→MDR

4. Send the valid address to the address code field of the instruction , Remember to do :(MDR)→ Ad(IR)

Memory is accessed through formal address , Register address accesses memory through register contents .

The memory itself cannot distinguish whether instructions or data are stored in the storage unit . Under the control of the controller , The computer reads the memory at different stages / When writing operations , The extracted code has different uses , The binary code read out in the fetch phase is the instruction , The code retrieved during execution may be data .

Instruction cycle data flow - Execution cycle

The task of the execution cycle is based on IR The opcodes and operands of the instruction words in the ALU Operations produce execution results . Different instructions have different execution cycles , So there is no unified data flow .

Instruction cycle data flow - Interrupt cycle

interrupt : Pause the current task to complete other tasks . In order to be able to resume the current mission , Need to save breakpoints . The stack is usually used to hold breakpoints , Here we use SP Represents the top of the stack address , hypothesis SP Point to the top element of the stack , The stack operation is to modify the pointer first , And then store the data .

1.CU Control will SP reduce 1, The modified address is sent to MAR Remember to do :(SP)-1 →SP,(SP) → MAR

It's essentially storing a breakpoint in a storage location , Suppose its address is a, So you can remember to do : a →MAR

2.CU Send out control signals , Start the main memory to write , Remember to do :1→w

3. Break point (PC Content ) Send in MDR, Remember to do :(PC)→ MDR

4.CU Control will interrupt the entry address of the service program ( Generated by the vector address forming unit ) Send in PC, Remember to do : Vector address →PC

Instruction execution scheme

An instruction cycle usually includes several time periods （ Execution steps ）, Each step completes part of the function of the instruction , Several sequential steps complete all the functions of this instruction .

programme 1． Single instruction cycle

Choose the same execution time for all instructions . Serial execution between instructions ; The instruction cycle depends on the execution time of the instruction with the longest execution time .

For instructions that could have been completed in a shorter time , Use this longer cycle to complete , It will reduce the running speed of the whole system .

programme 2． Multiple instruction cycles

Select different execution steps for different types of instructions . Serial execution between instructions ; Different number of clock cycles can be selected to complete the execution of different instructions .

Need more complex hardware design .

programme 3． Pipeline solution
Start an instruction at each clock cycle , Try to run multiple instructions at the same time , But they are in different steps of execution . Instructions are executed in parallel .

Data access

use CPU Characteristics of data path in internal bus mode ： Simple structure , Implement easily , Low performance , There are many conflicts .

Do not use CPU The data path of internal bus mode is characterized by ： Complicated structure , Large amount of hardware , It's not easy to achieve , High performance , There is basically no data conflict .

Single bus structure

An internal bus is the same component , Such as CPU Internal connection between the registers and the bus between the computing units ;

System bus refers to the components of the same computer system , Such as CPU、 Memory 、 Access and all kinds of l/O A bus that connects interfaces .

because ALU It's a combinational logic circuit , Therefore, the contents of the two inputs must be kept unchanged during the operation , And because of CPU The internal adopts single bus structure , So in order to get two different operands ,ALU One input of the is connected to the bus , The other input needs to be connected to the bus through a register . Besides ,ALU The output of can not be directly connected to the internal bus , Otherwise, its output is fed back to the input through the bus , Affect the operation result , Therefore, the output end needs to pass through a register （ A register used to temporarily store results ） Connected to the bus .

1． Data transfer between registers

For example PC Content sent to MAR, The process and control signal to realize the transmission operation are :

(PC)→Bus PCout It works ,PC Content delivery bus
Bus→MAR MARin It works , The bus content is sent to MAR

It's important to describe the flow of data

2. Main memory and CPU Data transfer between

such as CPU Read instructions from main memory , The process and control signal to realize the transmission operation are :

(PC)→Bus→MAR PCout and MARin It works , Current instruction address →MAR

1→R CU Issue a read command ( Through the control bus , There is no picture of ）

MEM(MAR)→MDR MDRin It works

MDR→Bus→IR MDRout and IRin It works , Current directive →IR

3. To perform arithmetic or logical operations

Like an addition instruction , The micro operation sequence and control signal are :

Ad(IR)→Bus→MAR MDRout and MARin Effective or AdlRout and MARin It works
1→R CU Issue a read command
MEM(MAR)→ cable →MDR MDRin It works

MDR→Bus→Y MDRout and Yin It works , Operands →Y
(ACC)+(Y)→z ACCout and ALUin It works ,CU towards ALU Send plus command
Z→ACC Zout and ACCin It works , result →ACC

Example

There is a single bus structure as shown in the figure , Analysis instructions ADD (RO),R1 The instruction flow and control signal of the system .

1. Analyze instruction function and instruction cycle

function :((R0))+(R1)→(R0)

Take the period 、 Interval period 、 Execution cycle

2. Write the instruction flow of each stage

Take the period : Public operation

Interval period : Complete the access operation , The addend is in main memory , The addend is already in the register R1 in .

Execution cycle : Complete the access operation , The addend is in main memory , The addend is already in the register R1 in .

Dedicated data path

Take the period

Example

Here's a simplified CPU Schematic diagram of main memory connection structure （ All multiplexers are omitted in the figure ）. There is a bound register （ACC)、 A status data register and other 4 A register : Main memory address register (MAR）、 Main memory data register (MDR）、 Program register （PC） And instruction registers （IR), The components and the connections between them represent data paths , The arrow indicates the direction of information transmission .

requirement ：

(1) Please write the figure a、b、c、d 4 The name of a register .

d It's automatic “+1”, yes PC

PC The content is the address , send MAR, so c yes MAR

b Connected to the micromanipulation signal generator , yes IR

The registers connected to main memory are MAR and MDR,c yes MAR, be a yes MDR

(2） Briefly describe the data path of the instruction in the diagram .

(PC)→ MAR

M(MAR)→MDR

(MDR)→IR

(3） Data is stored between arithmetic unit and main memory / Access

save / Take the data and put it in ACC in 、 Set the data address to MAR

take :

M(MAR)→ MDR

(MDR)→ALU →ACC

save :

(ACC)→ MDR

(MDR)→ M(MAR)

(4） Brief completion instructions LDA X The data path of （X Is the main memory address ）LDA The function of is (X)→ACC

X→MAR

M(MAR)→MDR

(MDR)→ALU →ACC

(5） Brief completion instructions ADD Y The data path of (Y Is the main memory address ）ADD The function of is (ACC)+(Y)→ACC

Y → MAR

M(MAR)→ MDR

(MDR)→ ALU,(ACC) → ALU

ALU →ACC

(6） Brief completion instructions STA Z The data path of (Z Is the main memory address ）STA The function of is (ACC)→Z

Z→ MAR

(ACC) →MDR

(MDR)→M(MAR)

Design of hardwired controller

Design steps :

1. Analyze the micromanipulation sequence of each stage

2. choice CPU Control mode of

3. Schedule micro operations

4. Circuit design

   (1) List the operation schedule

   (2) Write the simplest expression of micro operation command

   (3) Draw a logic diagram

Characteristics of hardwired controller :

• The more instructions , The more complex the design and Implementation , Therefore, it is generally used for RISC（ Reduced instruction set system )
• If you add a new instruction , Then the design of the controller needs to be greatly changed , Therefore, it is difficult to expand instructions .
• Due to the use of pure hardware to realize control , So the execution speed is very fast . The micromanipulation control signal is immediately generated by the combinational logic circuit .

Hardwired controllers

According to the instruction opcode 、 Current machine cycle 、 Beat signal 、 Machine condition , You can determine what should be emitted at this beat “ Micro command ”

Tips: Logical expressions are mathematical descriptions of circuits

Design of hardwired controller

Design steps ：

1． Analyze the micromanipulation sequence of each stage （ Value 、 Inter site 、 perform 、 Interrupt four stages ）： Determine which instructions are at what stage 、 Under what conditions will micro operations be used

2． choice CPU Control mode of ： Use fixed length machine cycle or variable length machine cycle ? Arrange several beats for each machine cycle ? Suppose synchronous control mode is adopted （ Fixed machine cycle ）, Arrange in a machine cycle 3 Beat time .

3． Schedule micro operations ： How to use 3 Complete all micro operations in the whole machine cycle in beats ?

4． Circuit design ： Determine the logical expression of each micro operation command , And realized by circuit

Analyze the micromanipulation sequence of each stage

The principle of scheduling micro operations

Principle one ： The sequence of micro operations should not be changed at will

Principle two ： Different micro operations of the controlled object should be completed in one beat

Principle three ： Micro operations that take up a short time should be completed in one beat as much as possible and allowed to have sequence

M( MAR )→MDR Access data from master , It is long , Therefore, one clock cycle is required to ensure the completion of micro operation

MDR→IR yes CPU Data transfer of internal registers , fast , Therefore, it can be completed immediately in one clock cycle OP(IR)→ID. That is, you can issue two micro commands at the same time .

Schedule micro operations - Interval period

Schedule micro operations - Execution cycle

Circuit design

Design steps :

1. List the operation schedule ： List finger taking 、 Inter site 、 perform 、 Interrupt cycle ,T0、T1、T2 There is
All micro operations that may be used

2. Write the simplest expression of micro operation command

3. Draw a logic diagram

Combinatorial logic design

Time operation table

Micromanipulation signal synthesis

Draw a logic diagram

Microprogrammed controllers

Design idea of microprogram controller

Program : It consists of a sequence of instructions

Microprograms : It consists of a sequence of microinstructions , Each instruction corresponds to a microprogram

Instructions are descriptions of program execution steps

Microinstructions are descriptions of instruction execution steps

Micro commands and micro operations correspond one by one , Microinstructions may contain multiple microcommands

Basic structure of microprogram controller

Working principle of microprogrammed controller

Fetching period microprograms are usually public , So if there is... In an instruction system n A machine command , be CM The number of microprograms is at least n+1 individual

Some early CPU、 Internet of things devices CPU Indirect addressing and interrupt functions are not provided , So this kind of CPU Address cycles may not be included 、 Interrupt the microprogram segment of the cycle

Tips: Physically , Take the period 、 The execution cycle looks like two microprograms , But logically, they should be regarded as a whole . therefore ,“ An instruction corresponds to a microprogram ” That's right

Microinstruction design

The format of microinstructions

Compatibility microcommand : Micro commands that can be completed in parallel .

Mutually exclusive microcommands : Micro commands that do not allow parallel completion .

Horizontal microinstructions

One microinstruction can define multiple parallelizable microinstructions .

advantage : Microprograms are short , Fast execution ;
shortcoming : Microinstruction length , Writing microprograms is troublesome .

Vertical microinstructions

A micro instruction can only define one micro command , The specific function is specified by the micro operation code field

advantage : Microinstructions are short 、 Simple 、 Be regular , Easy to write microprograms ;

shortcoming : Microprogram length , Slow execution , Low work efficiency .

Mixed microinstruction

Add some less complex parallel operations on the basis of vertical type .

Microinstructions are shorter , Still easy to write ; Microprograms are not long , Faster execution .

Encoding mode of microinstruction

The encoding mode of microinstruction is also called the control mode of microinstruction , It refers to how to encode the control field of microinstruction , To form a control signal . The goal of coding is to ensure the speed , Try to shorten the microinstruction word length .

Direct code （ Direct control ） The way

In the operation control field of the microinstruction , Each bit represents a micro operation command

Someone is “1” Indicates that the control signal is valid

advantage : Simple 、 intuitive , Fast execution , Good operation parallelism .

shortcoming : The microinstruction word length is too long ,n A micro command requires that the operation fields of the micro instruction have n position , Resulting in huge control and storage capacity .

Field direct encoding method

Divide the control fields of microinstructions into several “ paragraph ”, After each segment is decoded, a control signal is sent

The principle of micro command field segmentation :

① Mutually exclusive micro commands are divided into the same paragraph , Compatibility microcommands are divided into different segments .

② Each segment cannot contain too many bits of information , Otherwise, the complexity of decoding circuit and decoding time will be increased .

③ In general, each segment should have a status , Indicates that this field does not issue any micro commands . therefore , When the length of a field is 3 When a , At most, it can only mean 7 Two mutually exclusive micro commands , Usually use 000 It means no operation .

advantage : It can shorten the word length of microinstructions . shortcoming : It is necessary to send micro commands after passing the decoding circuit , Therefore, it is slower than direct encoding .

Example

The controller of a computer is controlled by microprogram , The operation control field in microinstruction adopts field direct coding method , share 33 A micro command , constitute 5 Mutex classes , Each contains 7、3、12、5 and 6 A micro command , Then how many bits does the operation control field have at least ?

The first 1 Mutually exclusive classes are 7 A micro command , To set aside 1 States indicate no operation , So we need to express 8 Different states , So we need 3 Binary bits .

And so on , Back 4 Mutually exclusive classes need to be taught 4、13、6、7 Different states , They correspond to each other 2、4、3、3 Binary bits .

Therefore, the total number of digits of the operation control field is 3＋2+4+3+3 = 15 position

Tips: If direct coding method is adopted , Then the control field needs 33 position

Field indirect encoding method

Some micro commands in one field need to be interpreted by some micro commands in another field , Because it is not directly decoded by the field , So it is called field indirect coding , Also known as implicit coding .

advantage : The microinstruction word length can be further shortened . shortcoming : It weakens the parallel control ability of microinstructions , Therefore, it is usually used as an auxiliary means of field direct coding .

The address formation method of microinstruction

1. The lower address field of the microinstruction indicates

Set a lower address field in the microinstruction format , The address of the subsequent microinstruction is directly indicated by the lower address field of the microinstruction , This way is also known as the way of judgment .

2. Form according to the opcode of the machine instruction

When the machine instruction is fetched to the instruction register , The address of the micro instruction is formed by the operation code through the micro address forming part .

3. Incremental counter method (CMAR )+1→CMAR

4. Branch transfer

Transfer mode : Specify the criteria ; Transfer address : Indicate the destination after successful transfer .

5. Test network

6. Microprogram entry address generated by hardware

First microinstruction address ― Produced by specialized hardware （ Use special hardware records to get the first address of the periodic microprogram ) Interrupt cycle ― Interrupt cycle microprogram first address generated by hardware （ Record with special hardware )

Example – The way of judging

Design of microprogram control unit

Design of microprogram control unit

obviously , Microprogrammed controllers are slower than hardwired controllers

Microprogramming classification

1. Static microprogramming and dynamic microprogramming

Static microprograms do not need to be changed , use ROM

Changing machine instructions dynamically by changing microinstructions and microprograms is conducive to simulation , use EPROM

2. Nanoprogramming

Basic concepts of nanoprogramming

Microprogramming uses microprograms to interpret machine instructions

Nanoprogramming uses nanoprograms to interpret microprograms

Comparison between hard wiring and microprograms

The basic concept of instruction pipeline

Ideal situation : Each stage takes the same time ; At the end of each stage, you can immediately enter the next stage .

Definition of instruction pipeline

The execution of an instruction can be divided into multiple stages （ Or process ). Depending on the computer , The specific classification is also different .

Fingering : according to PC Content access main storage , Take out an instruction and send it to IR in .

analysis : Decode the instruction opcode , Form the effective address of the operand according to the given addressing method and the content in the address field EA, And from the valid address EA Fetch operand from .

perform : According to the opcode field , Complete the functions specified in the instruction , That is, write the operation result to the general register or main memory .

characteristic : The hardware used in each stage is different .

Set index 、 analysis 、 perform 3 The time of each stage is equal , use t Express , Analyze according to the following execution methods n Execution time of instructions :

Traditional Feng · Neumann machine adopts sequential execution , Also known as serial execution .

advantage : Simple control , The cost of hardware is small .

shortcoming : The speed of executing instructions is slow , At any moment , There is only one instruction executing in the processor , The utilization rate of each functional component is very low .

advantage : The execution time of the program is shortened 1/3, The utilization rate of each functional component is significantly improved .

shortcoming : It needs to pay a high cost of hardware , The control process is also more complex than sequential execution .

Compared with sequential execution , The execution time of instructions is shortened by nearly 2/3. This is an ideal way to execute instructions , Under normal circumstances , There are 3 Instructions are executing .

notes : The execution process of each instruction can also be divided into 4 Or 5 Stages , Divide into 5 The second stage is a common practice .

Pipeline representation

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It is mainly used to analyze the instruction execution process and the factors affecting the pipeline

It is mainly used to analyze the performance of pipeline

Pipeline performance index

Throughput rate

Speedup ratio

efficiency

Five segment instruction pipeline

Machine cycle setting

There must be a buffer register behind each function segment of the pipeline , Or latch , Its function is to save the execution result of this flow segment , For the next flow section .

To facilitate the design of the assembly line , Take the time of each phase as the same , Take the longest time . That is, the machine cycle should be set to 100ns.
Ideally , Every machine cycle （ Function segment ） It only takes one clock cycle .

Five common types of instructions in exams :· Operation instruction 、LOAD Instructions 、STORE Instructions 、 Conditional transfer instructions 、 Unconditional transfer instructions

Only the last command enters ID After paragraph , The next command will start IF paragraph , Otherwise it will cover lF The contents of the segment latch

Operation class instruction execution process

Operation instruction

IF: according to PC From instructions Cache Take the command to lF Segment latch

ID: Take the operands to ID Segment latch

EX: operation , Store the results in EX Segment latch

M: Empty section

WB: Write the result back to the specified register

LOAD The execution of instructions

LOAD Instructions

IF: according to PC From instructions Cache Take the command to IF Segment latch

ID: Put the value of the base register in the latch A, Put the value of the offset in Imm

EX: operation , Get a valid address

M: From data cache And put it into the latch

WB: Write the fetched number back to the register

Usually ,RISC The processor only has “ Count LOAD” and “ Inventory STORE” Instructions to access main memory

STORE The execution of instructions

STORE Instructions

lF: according to PC From instructions Cache Take the command to IF Segment latch

ID: Put the value of the base register in the latch A, Put the value of the offset in Imm. Place the number to be saved in the B

EX: operation , Get a valid address . And put the latch B Put the contents of into the latch Store.

M: Write data Cache

WB: Empty section

The execution of conditional transfer instructions

Transfer class instructions often use relative addressing

Conditional transfer instructions

IF: according to PC From instructions cache Take the command to IF Segment latch

ID: The two numbers that are compared are put into the latch A、B; The offset is placed in Imm

EX: operation , Compare two numbers

M: The target PC Write the value back to PC

WB: Empty section

Many textbooks write back PC The functional segment of is called “WrPC paragraph ”, Its time-consuming ratio M The paragraph is shorter , Can be arranged in M Complete in a period of time

The execution of an unconditional transfer instruction

Unconditional transfer instructions

lF: according to PC From instructions Cache Take the command to IF Segment latch

ID: The offset is placed in Imm

EX: The target Pc Write the value back to PC（ The picture on the left is not complete )

M: Empty section

WB: Empty section

“WrPC paragraph ” Time ratio EX The paragraph is shorter , Can be arranged in EX Complete in a period of time .WrPC The sooner the section is completed , The more control conflicts can be avoided . Of course , There are also places where WB It took some time to modify PC Value

Example

Influencing factors and classification of instruction pipeline

There must be a buffer register behind each function segment of the pipeline , Or latch , Its function is to save the execution result of this flow segment , For the next flow section .

Factors affecting the assembly line

Structure related （ Resource conflict )

The conflict caused by multiple instructions competing for the same resource at the same time is called structure dependent .

terms of settlement :
1. The latter related instruction pauses for one cycle

2. Duplicate resource configuration : Data storage + Instruction memory

Data related （ Data conflict )

Data correlation refers to... In a program , There is a situation that the next instruction cannot be executed until the previous instruction is executed , Then these two instructions are data related .

terms of settlement :

1. Pause the instructions related to the encountered data and their subsequent instructions for one to several clock cycles , Continue until the data related problems disappear . It can be divided into hardware blocking (stall) And software insertion “NOP” The two methods .

2. Data bypass technology ： Forwarding mechanism

3. Compile optimization : Through the compiler to adjust the order of instructions to solve the data correlation .

Control related （ Control conflict )

When the pipeline encounters transfer instructions and other changes PC When the current is cut off due to the instruction of value , Will cause control related .

terms of settlement :

1. Branch prediction of branch instruction . Simple prediction （ Always guess ture or false） 、 Dynamic prediction （ Dynamically adjust according to historical conditions )

2. Prefetch the target instruction in the direction of successful and unsuccessful control flow

3. Accelerate and advance the formation of condition codes

4. Improve the accuracy of the transfer direction

Pipeline classification

1. Component functional level 、 Processor level and inter processor level pipeline

According to the level of pipeline , Pipeline can be divided into component function level pipeline 、 Processor level pipeline and inter processor pipeline .

Component function level pipelining is a pipelining method that combines complex arithmetic and logic operations . for example , Floating point addition operations can be divided into order differences 、 Antithetic order 、 Mantissa addition and result normalization 4 Sub process .

Processor level pipelining is to divide an instruction interpretation process into several sub processes , As mentioned above, take the finger 、 decoding 、 perform 、 Deposit and write back 5 Sub process .

Inter processor pipelining is a kind of macro pipelining , Each processor performs a specific task , The results obtained by each processor should be stored in the memory shared with the next processor .

2. Single function pipeline and multi-function pipeline

Functions that can be completed according to the assembly line , Assembly line can be divided into single function assembly line and multi-function assembly line .

Single function pipeline refers to a pipeline that can only realize one fixed special function ;

Multi function pipeline refers to a pipeline that can realize multiple functions at the same time or at different times through different connection methods between segments .

3． Dynamic pipeline and static pipeline

According to the connection mode between segments at the same time , Pipeline can be divided into static pipeline and dynamic pipeline .

Static pipeline means that at the same time , Each section of the pipeline can only work according to the connection mode of the same function .

Dynamic pipeline means that at the same time , When some segments are performing some operation , Other segments are performing another operation . This is good for improving the efficiency of the pipeline , But it will make the pipeline control very complicated .

4． Linear pipeline and nonlinear pipeline

Whether there is feedback signal between each functional section of the pipeline , Pipeline can be divided into linear pipeline and nonlinear pipeline .

In linear pipeline , From input to output , Each functional segment is allowed to pass only once , There is no feedback loop .

Nonlinear pipeline with feedback loop , From input to output , Some functional segments will pass through the pipeline several times , This pipeline is suitable for linear recursive operation .

Multi engine technology of pipeline

Superscalar Technology

Multiple independent instructions can be concurrent in each clock cycle

To configure multiple features

The execution order of instructions cannot be adjusted

By compiling optimization technology , Match instructions that can be executed in parallel

Superfluid technology

In another cycle （3 paragraph )

A function unit is used multiple times in a clock cycle （ 3 Time ）

The execution order of instructions cannot be adjusted

Solve optimization problems by compiling programs

Very long instruction words

The compiler digs out the potential parallelism between instructions , Combine multiple instructions that can operate in parallel into one

Extra long instruction word with multiple opcode fields （ Up to hundreds )

Multiple processing units are used

decoding 、 perform 、 Deposit and write back 5 Sub process .

Inter processor pipelining is a kind of macro pipelining , Each processor performs a specific task , The results obtained by each processor should be stored in the memory shared with the next processor .

2. Single function pipeline and multi-function pipeline

Functions that can be completed according to the assembly line , Assembly line can be divided into single function assembly line and multi-function assembly line .

Single function pipeline refers to a pipeline that can only realize one fixed special function ;

Multi function pipeline refers to a pipeline that can realize multiple functions at the same time or at different times through different connection methods between segments .

3． Dynamic pipeline and static pipeline

According to the connection mode between segments at the same time , Pipeline can be divided into static pipeline and dynamic pipeline .

Static pipeline means that at the same time , Each section of the pipeline can only work according to the connection mode of the same function .

Dynamic pipeline means that at the same time , When some segments are performing some operation , Other segments are performing another operation . This is good for improving the efficiency of the pipeline , But it will make the pipeline control very complicated .

4． Linear pipeline and nonlinear pipeline

Whether there is feedback signal between each functional section of the pipeline , Pipeline can be divided into linear pipeline and nonlinear pipeline .

In linear pipeline , From input to output , Each functional segment is allowed to pass only once , There is no feedback loop .

Nonlinear pipeline with feedback loop , From input to output , Some functional segments will pass through the pipeline several times , This pipeline is suitable for linear recursive operation .

Multi engine technology of pipeline

Superscalar Technology

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Multiple independent instructions can be concurrent in each clock cycle

To configure multiple features

The execution order of instructions cannot be adjusted

By compiling optimization technology , Match instructions that can be executed in parallel

Superfluid technology

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In another cycle （3 paragraph )

A function unit is used multiple times in a clock cycle （ 3 Time ）

The execution order of instructions cannot be adjusted

Solve optimization problems by compiling programs

Very long instruction words

[ Outside the chain picture transfer in …(img-xOjJL88w-1657716190909)]

The compiler digs out the potential parallelism between instructions , Combine multiple instructions that can operate in parallel into one

Extra long instruction word with multiple opcode fields （ Up to hundreds )

Multiple processing units are used