Allegro design entry CIS and OrCAD capture CIS relationship

Cadence（ Corporate name ）, The company is in EDA The field is in an international leading position , its PCB Design The field is well known in the market OrCAD and Allegro SPB Two brands , among OrCAD by 90 The acquisition of brands in the s ,Allegro SPB For its Private brand , Earlier versions were called Allegro PSD. After more than ten years of integration , at present Cadence PCB The field still implements double Brand strategy ,OrCAD Covering the middle and low-end market （ Easy to use tools can be obtained at a very low price , Mainly with Protel and Pads competition ）,Allegro SPB Covering medium and high-end markets （ And Mentor and Zuken competition ）

OrCAD The brand covers schematic tools OrCAD Capture/Capture CIS( Contains the function of component library management ), Schematic simulation tool PSpice（PSpiceAD、PSpiceAA）,PCB Layout Tools OrCAD PCB Editor（Allegro L edition ,OrCAD Originally owned OrCAD Layout stay 08 Sales have stopped worldwide since ）, Signal integrity analysis tool OrCAD Signal Explorer（Allegro SI The basic version of ）.

Allegro SPB The brand covers schematic tools Design Entry CIS( And OrCAD Capture CIS Exactly the same ),Concept HDL（Cadence Own schematic tools ）, Schematic simulation tool Allegro AMS Simulator（ namely PSpiceAD、PSpiceAA）,PCB Layout Tools Allegro PCB Editor（ Yes L、Performance、XL、GXL edition ）. Signal integrity analysis tool Allegro PCB SI（ Yes L、Performance、XL、GXL edition ）.

Allegro Available products include L、XL and GXL Three levels .

Allegro L The product line is PCB Design provides products aimed at solving mainstream design problems .Allegro XL The product family drives automatic control through integrated constraints and designs production capacity based on distributed teams , Provide advanced solutions to more complex and high-end design challenges PCB Design products . Allegro GXL The product line offers differentiated PCB Design products , It can cope with advanced packaging collaborative design and thousands of MHz signal integrity (SI) Cutting edge design challenges of analysis . 

Allegro Design Workbench XL It's a brand new product , for Allegro Design library provides component information and library management , It can automate the revision control of the Library , And provide the release including consistency information to the company design centers all over the world, such as RoHS Methods of known libraries . This can reduce the design cycle and component search by 50%. 
“ I admit that we need to manage our processes as efficiently as we manage our data .” Senior manager of design automation of Fujitsu network communication Gary Carter Say ,“Cadence Of Allegro Design Workbench Let us achieve these two points . It can meet our process and standards after simple setting , send Cadence Our technology integrates with other tools used in our design process . Our engineers also require current 、 Complete component information , Including technical and business data , for example ： cost 、 Lead time and availability 、 Be similar to RoHS Consistency data required for the indication of .Design Workbench Collect such information and enable engineers to see it from a regular perspective .” 

Allegro Design Publisher XL Can pass through Allegro Design Entry HDL The resulting design is published in intelligent and easy to browse PDF In file . This provides a way for the design team inside and outside the company to browse the design without Cadence A simple way to design access tools . 
This latest release is Allegro PCB SI A new board level bus analysis function is added , Can be shortened for example DDR2 Time of source synchronization signal verification of interfaces such as memory . Other enhancements related to the source synchronization interface include the on-chip terminator (ODT) Support for 、 Union of clocks 、 Filtered signal of bus 、 Board level customization incentive combination 、 And installation and control time report . in addition ,Allegro PCB Editor It is also enhanced to reduce the time of identifying critical Networks , These networks may have return path problems .