Catalog

1. clock frequency

2. IO Set up

3. SPI0_SETUP Set up

4.  SPI0_CTRL

5. Read and write data

CH549/CH548 Have 1 A hardware SPI Interface , Support master / Slave mode , Only the main mode is discussed here . in addition ,SPI The main mode only supports mode 0 And pattern 3, Consider commonality , Only set to mode 0.

1. clock frequency

CH549/CH548 Through registers SPI0_CK_SE（ The default is 0x20） Set the frequency , Up to half of the main frequency of the system .datasheet The calculation formula is not stated in , Guess it is

freq = Fsys / (SPI0_CK_SE + 1)

2. IO Set up

    P1_MOD_OC &= ~(bMOSI | bSCK);
    P1_DIR_PU |= (bMOSI | bSCK);                 //SCS, MOSI, SCK Set push-pull output 
    P1_MOD_OC |= bMISO;                                 //MISO  Pull up input 
    P1_DIR_PU |= bMISO;

here CS The feet are P1.4, Actually, it can be replaced by any IO,SCS Function is used for slave mode .

3. SPI0_SETUP Set up

Valid bits in main mode ：

  Generally, interrupt is not used , It's usually MSB High in the former , So these bits are 0.

4.  SPI0_CTRL

  Set up MOSI and SCK For export （ position 6 And place 5 Set to 1）, Pattern 0（ position 3 Set to 0）, Three wire mode （ position 2 Set to 0）

SPI0_CTRL = (bS0_MOSI_OE | bS0_SCK_OE);

5. Read and write data

SPI0_DATA = (wrBuf != NULL) ? wrBuf[i] : 0xff;
while(S0_FREE == 0);
if(rdBuf != NULL)
    rdBuf[i] = SPI0_DATA;

SPI It's full duplex , So the read-write synchronization is completed .SPI0_DATA Registers are physically separate FIFO, The reading operation corresponds to
Receive data FIFO; Write operation corresponds to sending data FIFO.

S0_FREE It's a register SPI0_STAT Bit 3, Addressable addressing