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Constraints in vivado that you can't understand
2022-07-18 14:54:00 【IC learners】
from FLASH Loader
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
Set from flash Load the program into FPGA The bit width of
Reference resources :https://zhuanlan.zhihu.com/p/133819529
The pin is suspended
The pin is suspended
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
UCIO #1 7 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: b_pad_gpio_porta[7], b_pad_gpio_porta[6], b_pad_gpio_porta[5], b_pad_gpio_porta[4], b_pad_gpio_porta[3], b_pad_gpio_porta[2], b_pad_gpio_porta[1].
I'm worried about whether the software will randomly assign constraints to suspended pins
This operation is very dangerous , adopt implement Can be seen in ,vivado Pins are randomly assigned .
Use the default level
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
7 out of 12 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: b_pad_gpio_porta[7], b_pad_gpio_porta[6], b_pad_gpio_porta[5], b_pad_gpio_porta[4], b_pad_gpio_porta[3], b_pad_gpio_porta[2], b_pad_gpio_porta[1].
It is recommended not to let the pin hang !!!
Unused pin level management
To overcome the LED Inexplicably lit
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
Compress bit file size
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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