Start of u-boot S analysis (II)

       This section continues the previous analysis lowlevel_init function . So where on earth is this function ？ Let's take another look at the linker script defined earlier .text paragraph .

.text:
	{
    
	  cpu/s5pc11x/start.o	(.text)
	  cpu/s5pc11x/s5pc110/cpu_init.o	(.text)
	  board/samsung/x210/lowlevel_init.o	(.text)
      cpu/s5pc11x/onenand_cp.o      (.text)                 
      cpu/s5pc11x/nand_cp.o (.text)                     
      cpu/s5pc11x/movi.o (.text) 
      common/secure_boot.o (.text) 
	  common/ace_sha1.o (.text)
	  cpu/s5pc11x/pmic.o (.text)
	  *(.text)
	}

       Here are clear instructions lowlevel_init It may appear in lowlevel_init.o In the corresponding file （ It can also be in cpu_init.o Search in the corresponding file , But I can't find it at all ）, We turn on board/samsung/x210/lowlevel_init.S You can find our objective function in the file , Let's just talk about some key parts .

Check the reset state

/* check reset status */

ldr	r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
ldr	r1, [r0]
bic	r1, r1, #0xfff6ffff
cmp	r1, #0x10000
beq	wakeup_reset_pre
cmp	r1, #0x80000
beq	wakeup_reset_from_didle

• Various operations can be carried out in different states , For example, hot start does not require initialization DDR.

Turn off the watchdog

ldr	r0, =ELFIN_WATCHDOG_BASE	/* 0xE2700000 */
mov	r1, #0
str	r1, [r0]

Development board lock

	/* PS_HOLD pin(GPH0_0) set to high */
	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + PS_HOLD_CONTROL_OFFSET)
	ldr	r1, [r0]
	orr	r1, r1, #0x300	
	orr	r1, r1, #0x1	
	str	r1, [r0]

• The so-called locking is to lock the signal , Keep it high or low
• The following is the circuit design of the power module of the development board , A voltage stabilizing chip is connected between the input power supply and the power supply of the development board MP1482, This chip has a EN（Enable） Pin , This pin can let the voltage stabilizing chip output （ For high voltage ） Or turn off the output （ Low power level ）.
  
• EN The pin has a VDD_IN Power input , But this power input is
  Blocked , therefore EN Whether the pin has voltage depends on whether the hardware is conductive , Whether it has access depends on the following 1 This point
• When POWER After the key is pressed ,1 Point is connected , be EN The pin generates voltage . When the key is released, the voltage disappears
• When EINT0 Pin for POWER_LOCK High voltage usually ,1 Points can also be connected .EN Voltage will also be generated
• EINT1 Pins are used to interrupt , Provide to CPU Used to wake up
• Summarized below
  
• According to the comments in the code , We search in the data book PS_HOLD, Found the following definition
  
• From the data book above, we can see that only the 0,8,9 It makes sense , When the first 0 Set to 1 You can only use PS_HOLD_CONTROL function , The first 9 Bits define the direction of the signal , It is exported, so it is set to 1, And we need to set it to high level , So the first 8 It's also for 1
• Therefore, to realize the lock setting function, we will 0,8,9 All bits are set to 1 that will do , Let's look at the code

1. ldr r0, =(ELFIN_CLOCK_POWER_BASE + PS_HOLD_CONTROL_OFFSET) Write the address to r0 register
2. ldr r1, [r0] Read with register indirect addressing r0 The value in is stored in r1 in
3. orr r1, r1, #0x300 take r1 The value of and 0x300 To perform a bit or operation , The result is deposited in r1 in ,0x300 In fact, that is 11 0000 0000, Therefore, the eighth and ninth bits are set to 1, The remaining values remain unchanged
4. orr r1, r1, #0x1 The functions above are the same , The result is to put the number 0 Bit is set to 1, In this way, the second 0,8,9 The bits are all set to 1 了
5. str r1, [r0] Write it back

• This completes the lock setting function of the development board . When the program finishes executing this code, it will always remain in the power state , If you unregister this code , You must press and hold the power key to power the development board

Determine the current code execution location

	/* when we already run in ram, we don't need to relocate U-Boot. * and actually, memory controller must be configured before U-Boot * is running in ram. */
	ldr	r0, =0xff000fff
	/* take pc Some bits in the value of are cleared , Some special bits are assigned to r1（r0 In Chinese, it means 1 The bits are cleared ）, amount to  r1 = pc & ~(0xff000fff).*/
	bic	r1, pc, r0		/* r0 <- current base addr of code */
	ldr	r2, _TEXT_BASE		/*  Load link address to r2, And then r2 The corresponding bit of 0 What's left is special positioning  r1 <- original base addr in ram */
	bic	r2, r2, r0		/* r0 <- current base addr of code */
	cmp     r1, r2                  /* compare r0, r1 */
	beq     1f			/* r0 == r1 then skip sdram init */

• The purpose of these lines of code is to determine where the current code is executing SRAM In or out DDR in
• BL1（uboot The previous part of ） stay SRAM One of them , stay DDR There is also a share of , Therefore, if it is a cold start, the current code should be in SRAM Running in BL1, If it is a low-power state reset, it should be in DDR Running in .
• We determine the address of the current running code to guide the operation of the following code . For example, in lowlevel_init.S in , Determining the running address of the current code is to determine whether to perform clock initialization and initialization DDR Code for . If the current code is in SRAM in , It means cold start , So the clock and DDR All need to be initialized ; If the current code is in DDR in , Then it means hot start, then the clock and DDR You don't have to initialize again .
• adopt cmp Judge , If equal, it is in DDR in , Inequality is in SRAM in
• beq The instruction means to jump if they are equal ,1 Representative label ,f Represents looking down ,b It means looking forward （ If there is b Words ）

The rest

• Clock initialization system_clock_init
• DDR initialization mem_ctrl_asm_init
• Serial initialization uart_asm_init, After initialization, you will see ”O" character
• lowlevel_init Output before returning "K" character