Abstract

• In the use of case Statement and multiple outputs , Every case Branch statements should give the assignment of all outputs , Otherwise, the circuit will synthesize the latch .
• In the following example , Through the variable sel To select four outputs up、down、left、right Which is assigned 1, Two code implementation methods are given .
• In the first implementation , Every case The branch statement of gives all the output values .
• In the second way , Although the initial value of the variable is specified , But every case Statement does not assign values to all variables .

Code

`timescale 1ns / 1ps

module top(
    input  [1:0] sel,
    input  [1:0] sel1,
    
    output reg up,
    output reg down,
    output reg left,
    output reg right,
    
    output reg up1=0,
    output reg down1=0,
    output reg left1=0,
    output reg right1=0
);

[email protected](*)begin
    up=0;down=0;right=0;left=0;
    case(sel)
        2'b00:up=1'b1;
        2'b01:down=1'b1;
        2'b10:right=1'b1;
        2'b11:left=1'b1;
        default:up=1'b1;
    endcase
end

[email protected](*)begin
    case(sel1)
        2'b00:up1=1'b1;
        2'b01:down1=1'b1;
        2'b10:right1=1'b1;
        2'b11:left1=1'b1;
        default:up1=1'b1;
    endcase
end    

endmodule

Integrated circuit

It can be seen from the integrated schematic diagram , The second code implementation method produces LDCE（ Asynchronously cleared latch）