Mux256to1v,Hadd，Fadd

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

有以下几种方法

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
assign out = in[sel*4 +: 4];// 从 sel*4 开始，选择比特序号大于sel*4 的 4 位比特，相当于[sel*4+3:sel*4]
endmodule

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
assign out = in[sel*4+3 -: 4];	// 从 sel*4+3 开始，选择比特序号小于 sel*4+3 的 4 位比特，相当于[sel*4+3:sel*4]
endmodule

 Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b,
    output cout, sum );
    assign {cout,sum} = a + b;
endmodule

 Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign{cout,sum} = a + b + cin;
endmodule