Processing method of CDC in SDC

Recently in to see S Jiamou IP About CDC To deal with the SDC Constrained , I saw some useful knowledge points and SDC constraint , Here is a summary .

1. In common understanding , We expect the synthesis tool not to check and optimize the timing path between asynchronous clocks , So only in sdc Set it to async, for example , When clk_a and clk_b For asynchronous clock , You can set it as follows ：
set_clock_groups -asynchronous -group clk_a -group clk_b

But in real projects , You also need to add some special constraints to the asynchronous clock path . among set_max_delay and set_min_delay Is a common practice ,set_max_delay Will be used in the destination register (destination flop) Of setup check,set_min_delay Will be used in the destination register (destination flop) Of hold check.set_max/min_delay Need to add -ignore_clock_latency switch , Ensure that when calculating the asynchronous clock path delay when , Don't consider clock tree latency（ Only in CTS And then there is ）

2. In order to make set_max/min_delay take effect , There are two things to note ：
1） Set up set_max/min_delay The path of , Cannot add set_false_path, Because this setting has a higher priority
2） Asynchronous clocks cannot be used as in the previous example , Just set up async, Instead, join -allow_paths, The complete command is as follows ：
set_clock_groups -asynchronous -allow_paths -group clk_a -group clk_b

Here are Synopsys Synthesis Commands Explanation of this option in

-allow_paths
Enable the timing analysis between specified clock groups. If this option is not specified, the timing analysis among the defined clock groups are disabled. This option can be used with asynchronous clock groups only.

3. When gray code data is transferred between asynchronous clock domains , And the destination clock domain uses a two-stage synchronizer （ register ） When sampling data , should set_max_delay For a source clock cycle ,set_min_delay by 0. This ensures that only gray code will be sampled in the destination clock domain .

4. When asynchronous clocks are passed between domains Qualifier-based Data Bus Signal when , should set_max_delay by ( Synchronous series -0.5)* Destination clock cycle ,set_min_delay by 0. This ensures that only stable data will be sampled in the destination clock domain .

5. except 3.4. In addition to the two kinds of data mentioned in , Other CDC Path should set_max_delay Clock cycles for a purpose ,set_min_delay by 0. The purpose of this move is explained in the relevant documents （ I don't quite understand ）

maintain the assumptions for a safe CDC implementation

6. Some quasi-static data , For example, registers that are configured after power on and will not change later , It can be considered as a pure asynchronous path , Sure set_false_path

7. asynchronous FIFO in , May use some standard cell To ensure the timing of the correlation path , We don't want these cell Logic optimization by comprehensive tools , So we need to be in sdc Add set_size_only constraint , Here are Synopsys Synthesis Commands Explanation of the command in

When the set_size_only command is issued with the true value on a cell, optimization of that part is treated specially. In general, this command directs synthesis to perform only a sizing operation on a cell. The set_size_only command can be used only on leaf cell instances.